Conventional CCD image sensors are fabricated using multiple layers of polysilicon separated by inter-poly dielectrics (oxides). A portion of a conventional CCD image sensor is shown in FIG. 1. FIG. 1 depicts a three-phase polysilicon gate CCD image sensor structure having a plurality of gates 2 separated from each other by a layer of inter-poly dielectric 4. The polysilicon gates 2 also overlay an insulating layer of oxide 6 which substantially overlays a silicon substrate 8. The insulating layers 4 and 6 electrically isolate the gates 2 from each other and from the substrate 8, respectively. The gates 2 are of three types, each type manufactured using a distinct layer of polysilicon. The first type, called poly-1 10, is generally flat on both sides. The second type, called poly-2 12 has an overlap 14 on one side which overlaps one side of the poly-1 gate 10. The third type, called poly-3 16, has overlaps 18, 20 on both sides that overlap the poly-2 gate 12 and the poly-1 gate 10. Poly-1 gate 10, poly-2 gate 12, and poly-3 gate 16, portions of inter-poly-oxide layers 4, an underlying portion of oxide layer 6, and a portion of the silicon substrate 8 constitute a three phase CCD pixel 22.
This type of multiple poly CCD pixel structures can be manufactured using conventional photolithographic processes. The three-phase poly gate structure shown in FIG. 1 can be manufactured using the following procedure. In a first step, a dielectric layer 6 is deposited or grown on the silicon substrate 8. A first layer of polysilicon is deposited substantially overlying the dielectric layer 6. Using a conventional photolithographic method and anisotropic etching, the poly-1 gates 10 are defined. This is followed by growing or depositing a first layer of inter-poly dielectric 4 substantially overlaying the poly-1 gates 10. Then, a second layer of polysilicon is deposited substantially overlaying the inter-poly dielectric 4 and the poly-1 gates 10, followed by photolithography and etching to define the poly-2 gates 12. Another portion of the inter-poly dielectric 8 is grown or deposited overlying both the poly-1 gates 10 and the poly-2 gates 12. Then, a third layer of polysilicon is deposited substantially overlaying the inter-poly dielectric 4, the poly-1 gates 10, and the poly-2 gates 12, followed by photolithography and anisotropic etching to define the poly-3 gates 16. Another portion of the inter-poly dielectric 8, followed by an insulating layer like PPSG, is deposited overlying poly-1 gates 10, poly-2 gates 12, and poly-3 gates 16 to complete the process.
In operation, charge is collected under any one of the polysilicon gates 10, 12, 16, and subsequently transferred to a another of the polysilicon gates 10, 12, 16 by the application of appropriate bias to each of the polysilicon gates 10, 12, 16. The inter-poly dielectric layer 8 keeps the gates 10, 12, and 16 isolated from each other so that different potentials can be applied to different types of gates. As a byproduct, the inter-poly dielectric 8 creates potential barrier “bumps” which the charges must overcome to be successfully transferred to a subsequent gate. If the separation between the gates is great, i.e., the inter-poly-oxide thickness is too large, then collected charge cannot clear the “bump” and the transfer becomes less efficient or does not occur. If the inter-poly dielectric thickness is too small, then a premature dielectric breakdown can occur between gates.
Charge transfer between phases depends on the spacing of polysilicon gate edges and resulting electric fringing fields between them. A desirable thickness that produces efficient charge transfer is about 0.2 microns between gates. It would also be desirable to create the polysilicon gates 10, 12, 16 using only a single layer of polysilicon and no overlap. Unfortunately, prior art methods of manufacturing gates with single layer polysilicon cannot achieve 0.2 micron gaps using conventional lithographic tools in a highly reproducible manner. This problem is alleviated by the multi-layer polysilicon technique, where it is relatively easy to define 0.2 micron gaps via the deposition or growing of inter-poly-oxide layers 8 and overlapping gates. These polysilicon overlaps add capacitance, which in turn, slows down the operation of the CCD. Imagers employing overlapping multiple poly gates are susceptible to ESD damage during the manufacturing process and the edges of the gates can lift from the surface of the oxide (dielectric) layer 8 due to the subsequent oxidation of the patterned polysilicon, producing uneven inter gate gap thicknesses which results in premature electrical breakdown. There are more sophisticated photolithographic tools available in the prior art which can define inter-gate gaps of 0.2 microns, but these tools are themselves expensive.
Accordingly, what would be desirable, but has not yet been provided is a method for manufacturing CCD image sensors having single layer poly-silicon gates employing conventional photolithographic techniques and equipment.